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2021•DEStech Transactions on Materials Science and EngineeringRequires access

A High Speed and Wide Frequency Division Range Mixed-Signal Pulse Swallow Frequency Divider for Phase-Locked-Loop

Yimeng Zhao, Haiyang Quan, Zengrong Liu

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Abstract

A frequency divider for a high speed and wide band Phase- Locked-Loop (PLL) which output frequency range is from 6 GHz to 12.5 GHz, is described. The designed mixed-signal swallow pulse divider mainly includes a divide-by-8/9 dual-modulus prescaler which is based on source coupled logic (SCL) structure for achieving high speed frequency division, and a 3-bit swallow counter and an 8-bit programmable counter to achieve wide range division ratio. This divider is fabricated in 65nm CMOS process and the power supply voltage is 1.25 V. The simulation results show that the power consumption of this divider is 5.34 mW. And the divider can achieve a continuous integer division ratio from 72 to 2047 in the PLL tuning range.

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What this paper is about

A frequency divider for a high speed and wide band Phase- Locked-Loop (PLL) which output frequency range is from 6 GHz to 12.5 GHz, is described. The designed mixed-signal swallow pulse divider mainly includes a divide-by-8/9 dual-modulus prescaler which is based on source coupled logic (SCL) structure for achieving high speed frequency division, and a 3-bit swallow counter and an 8-bit programmable counter to achieve wide range division ratio. This divider is fabricated in 65nm CMOS process and the power supply voltage is 1.25 V. The simulation results show that the power consumption of this divider is 5.34 mW. And the divider can achieve a continuous integer division ratio from 72 to 2047 in the PLL tuning range.

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Available abstract

A frequency divider for a high speed and wide band Phase- Locked-Loop (PLL) which output frequency range is from 6 GHz to 12.5 GHz, is described. The designed mixed-signal swallow pulse divider mainly includes a divide-by-8/9 dual-modulus prescaler which is based on source coupled logic (SCL) structure for achieving high speed frequency division, and a 3-bit swallow counter and an 8-bit programmable counter to achieve wide range division ratio. This divider is fabricated in 65nm CMOS process and the power supply voltage is 1.25 V. The simulation results show that the power consumption of this divider is 5.34 mW. And the divider can achieve a continuous integer division ratio from 72 to 2047 in the PLL tuning range.

Key concepts: Frequency divider, Current divider, Phase-locked loop, Frequency multiplier, Wilkinson power divider, Division (mathematics), Voltage divider, Electrical engineering

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