2011Microelectronics & ComputerRequires access

6 GHz Novel High-Speed Low-Power Frequency Divider

Zhuo Ma

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Abstract

High speed frequency divider is widely used in PLL-based frequency synthesizers.A configurable pulse-swallow divider with the range from 2 to 256 is presented in this article.The divider based on an improved divided-by-2 architecture without any conventional dual-modulus prescaler is designed to reduce power consumption and chip area.Implemented in 65nm CMOS process,post-layout simulation results show that the divider can work as high as 6GHz stably while the max power dissipation is no greater than 1.3mW.

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What this paper is about

High speed frequency divider is widely used in PLL-based frequency synthesizers.A configurable pulse-swallow divider with the range from 2 to 256 is presented in this article.The divider based on an improved divided-by-2 architecture without any conventional dual-modulus prescaler is designed to reduce power consumption and chip area.Implemented in 65nm CMOS process,post-layout simulation results show that the divider can work as high as 6GHz stably while the max power dissipation is no greater than 1.3mW.

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Available abstract

High speed frequency divider is widely used in PLL-based frequency synthesizers.A configurable pulse-swallow divider with the range from 2 to 256 is presented in this article.The divider based on an improved divided-by-2 architecture without any conventional dual-modulus prescaler is designed to reduce power consumption and chip area.Implemented in 65nm CMOS process,post-layout simulation results show that the divider can work as high as 6GHz stably while the max power dissipation is no greater than 1.3mW.

Key concepts: Frequency divider, Computer science, Current divider, Chip, CMOS, Dissipation, Power (physics), Power dividers and directional couplers

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