FIR Digital Filter Design and Simulation Using Verilog HDL

The basic structure and hardware architecture of FIR digital filter are analyzed,following briefly introduction to the advantages and disadvantages of different kinds of methods to implement FIR DF.Combined with the FPGA product characteristics of Altera ' s Stratix series,the process and methods of digital logic design using Verilog HDL are presented in a 8-order FIR DF design based on MAC.The HDL code is written and synthesized in QuartusⅡ and the design is verified and simulated by the QuartusⅡ' s integrated simulator.