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Algorithm and Implemention with FPGA of RS(255,223) Decoder According to CCSDS

Tingjiang Yan

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Abstract

The parameters and decoder structure of RS(255,223)according to CCSDS specification is introduced.It is given that the reformulated inversionless BM algorithm which is used to solve the key equation.The decoder based on this algorithm is designed and implemented with Verilog HDL.As test results shown,the decoder described in this paper decrease resource usage in a great deal at high speed.

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What this paper is about

The parameters and decoder structure of RS(255,223)according to CCSDS specification is introduced.It is given that the reformulated inversionless BM algorithm which is used to solve the key equation.The decoder based on this algorithm is designed and implemented with Verilog HDL.As test results shown,the decoder described in this paper decrease resource usage in a great deal at high speed.

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Available abstract

The parameters and decoder structure of RS(255,223)according to CCSDS specification is introduced.It is given that the reformulated inversionless BM algorithm which is used to solve the key equation.The decoder based on this algorithm is designed and implemented with Verilog HDL.As test results shown,the decoder described in this paper decrease resource usage in a great deal at high speed.

Key concepts: Verilog, Computer science, Field-programmable gate array, Soft-decision decoder, Key (lock), Decoding methods, Resource (disambiguation), Algorithm

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