Design of Bit Parallel RS Encoder Based on Weak Dual Basis

The high speed design problem of RS encoder is discussed.The presentation of finite field element under weak dual basis is studied. Based on the calculation method over the optimal weak dual basis, the design process for the finite field bit parallel multiplier is given and Reed Solomon (RS)(255, 233) encoder is constructed by use of this multiplier. The quantitative analysis results for RS (255, 233) encoder complexity have shown that the reduction of the design complexity for the bit parallel multiplier under weak dual basis is convenient for the implementation of VLSI. The data throughput of the encoder can be a higher value and is good for the highs speed applications.