Design of Bit-Parallel Reed-Solomon Encoder Based on Dual Basis
Liu Chang-yin
Abstract
Liu Chang-yin
Abstract
Reed-Solomon (RS) codes, which have been adopted by many international standards, have found increasing application in such areas as satellite and mobile communications, data storage and transmission, video systems, etc. The development of efficient encoding scheme is thus of great importance especially for high speed applications. This paper is concerned with the RS encoder over a dual basis, and RS encoder in DVB-C system was implemented as a example. Referring to Bit-Serial Berlekamp multiplier, the circuit was simplified into gates circuit, and the encoder was realized as bit-parallel. The proposed RS encoder has the advantages of high throughput, low hardware requirements and is suitable for FPGA implementation.
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Reed-Solomon (RS) codes, which have been adopted by many international standards, have found increasing application in such areas as satellite and mobile communications, data storage and transmission, video systems, etc. The development of efficient encoding scheme is thus of great importance especially for high speed applications. This paper is concerned with the RS encoder over a dual basis, and RS encoder in DVB-C system was implemented as a example. Referring to Bit-Serial Berlekamp multiplier, the circuit was simplified into gates circuit, and the encoder was realized as bit-parallel. The proposed RS encoder has the advantages of high throughput, low hardware requirements and is suitable for FPGA implementation.
Key concepts: Encoder, Computer science, Computer hardware, Field-programmable gate array, Encoding (memory), Multiplier (economics), Reed–Solomon error correction, Arithmetic