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Design for RS (255,223) encoder based on CCSDS criteria

Huisheng Zhang

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Abstract

This paper researched a kind of Reed-Solomon (RS) encoder under CCSDS standard,which used time domain coding method.It analysed the principle of Reed-Solomon(RS) encode,the design of basic unit circuit,including Galois field adder and multiplier,and addressed the application method of parallel multiplier with constant coefficients under the natural base.This paper designed a RS (255,223) encoder with symmetric coefficients of generator polynomial under the QuartusⅡ5.0 environment.In addition,figured out the simulation results,and results of the output were correct by the test.The RS (255,223) encoder designed by this method not only effectively simplifies the control unit and has the regular modular structure,but also is easy for FPGA implementation and can be used in high-speed occasions.

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What this paper is about

This paper researched a kind of Reed-Solomon (RS) encoder under CCSDS standard,which used time domain coding method.It analysed the principle of Reed-Solomon(RS) encode,the design of basic unit circuit,including Galois field adder and multiplier,and addressed the application method of parallel multiplier with constant coefficients under the natural base.This paper designed a RS (255,223) encoder with symmetric coefficients of generator polynomial under the QuartusⅡ5.0 environment.In addition,figured out the simulation results,and results of the output were correct by the test.The RS (255,223) encoder designed by this method not only effectively simplifies the control unit and has the regular modular structure,but also is easy for FPGA implementation and can be used in high-speed occasions.

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Available abstract

This paper researched a kind of Reed-Solomon (RS) encoder under CCSDS standard,which used time domain coding method.It analysed the principle of Reed-Solomon(RS) encode,the design of basic unit circuit,including Galois field adder and multiplier,and addressed the application method of parallel multiplier with constant coefficients under the natural base.This paper designed a RS (255,223) encoder with symmetric coefficients of generator polynomial under the QuartusⅡ5.0 environment.In addition,figured out the simulation results,and results of the output were correct by the test.The RS (255,223) encoder designed by this method not only effectively simplifies the control unit and has the regular modular structure,but also is easy for FPGA implementation and can be used in high-speed occasions.

Key concepts: Computer science, Encoder, Multiplier (economics), Computer hardware, Field-programmable gate array, Adder, Modular design, Coding (social sciences)

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