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Design and Implementation of RS Decoder Based on FPGA

Jiayou Song

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Abstract

For the problems as complex RS decoding process,low decoding speed and expensive specific RS decoder,and with RS(31,15) code adopted by JTIDS terminal as an example,the RS decoding theory based on the improved no-inversion BM iteration algorithm is described.With FPGA platform and Verilog HDL,the submodules of the RS decoder are designed.The correction ability of the RS decoder is simulated and verified with the software of Quartus II 6.0.And the parameterized and modularized design of RS decoder is thus achieved.

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What this paper is about

For the problems as complex RS decoding process,low decoding speed and expensive specific RS decoder,and with RS(31,15) code adopted by JTIDS terminal as an example,the RS decoding theory based on the improved no-inversion BM iteration algorithm is described.With FPGA platform and Verilog HDL,the submodules of the RS decoder are designed.The correction ability of the RS decoder is simulated and verified with the software of Quartus II 6.0.And the parameterized and modularized design of RS decoder is thus achieved.

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Available abstract

For the problems as complex RS decoding process,low decoding speed and expensive specific RS decoder,and with RS(31,15) code adopted by JTIDS terminal as an example,the RS decoding theory based on the improved no-inversion BM iteration algorithm is described.With FPGA platform and Verilog HDL,the submodules of the RS decoder are designed.The correction ability of the RS decoder is simulated and verified with the software of Quartus II 6.0.And the parameterized and modularized design of RS decoder is thus achieved.

Key concepts: Computer science, Soft-decision decoder, Field-programmable gate array, Decoding methods, Verilog, Parameterized complexity, Code (set theory), Process (computing)

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