Synchronous Design Techniques for Multi-clock Domains in Integrated Circuit

During the process of communication between different clock domains,metastability is likely to happen.This paper discusses several applications of different synchronizers in IC asynchronous design.Asynchronous FIFO is applied to the design of asynchronous data buffer between the interface and the core of ATM communication chip.The results of simulation show that the method can increase the reliability as well as realize the desired function.