An Implementation of Communicating Data between Multi-clock Domain Based on FPGA

The paper analyses the metastability which is caused by communicating data between multi-clock domain and effect of metastability to the circuit.For example,the design of asynchronous parallel communication interface chip is described to make use of synchronizer and FIFO to transfer the data band from 8 bits to 16bits between two clock domain in details.The circuit is simulated on a Modelsim5.7 with Xilinx ISE6.0 software and good test result has gotten.