The Solution of Metastability in Asynchronous System Design based on FPGA

In this paper, we will illustrate the mechanism of metastability issues in ASICs designs that are driven by multiple asynchronous clocks.In order to solve this problem, effective synchronization method is described first.Using the proposed design techniques and optimization methods, metastability could be controlled and system reliability could be improved.We provide the structure of the system to show the process of the workflow, and then analyzed the high and low impact on the system.We divided the system into different parts, and designed the schematic for each part to realize the system.After all modules have been completed, we designed an experiment to test the performance of the system.The test results showed that the system is running well which has some practical value.