Zhiying Wang
Abstract
An asynchronous integrated circuit design flow based on macro cells is described.Using this design flow,a 32-bit 4-sector pipelined asynchronous adder in ASIPs is designed.Compared with the synchronous version,the asynchronous adder has the similar performance and the advantage of power consumption.
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An asynchronous integrated circuit design flow based on macro cells is described.Using this design flow,a 32-bit 4-sector pipelined asynchronous adder in ASIPs is designed.Compared with the synchronous version,the asynchronous adder has the similar performance and the advantage of power consumption.
Key concepts: Computer science, Adder, Asynchronous communication, Asynchronous circuit, Design flow, Serial binary adder, Asynchronous system, Computer architecture