Comparison of Asynchronous vs. Synchronous Design Technologies Using a 16-Bit Binary Adder

Asynchronous design is a promising technology that is gaining more and more attention. It's claimed to offer several advantages over synchronous designs including high-speed performance, low power, and modularity. To compare asynchronous to synchronous design technologies, two 16-bit binary adders are designed. All design decisions are based on high-speed performance with area and power as secondary concerns. Architectures are chosen for each adder design that enables the given technology. The asynchronous design is optimized for the best case average delay and the synchronous design is optimized for the best worse case delay. The asynchronous 16-bit adder is implemented with a carry look-ahead architecture using 2-bit blocks. The carry-select architecture is selected for implementing the synchronous 16-bit adder. The two 16-bit adder designs are compared using two experiments. The first experiment measures the computation delay for 10,000 random input permutations. The synchronous design worse case delay is compared to the asynchronous average delay. The asynchronous adder average delay outperforms the synchronous worse case delay by more than 250 ps. In the second experiment the 16-bit binary adders are implemented into an adder test-bench system, and 32 consecutive additions are performed. In this experiment the synchronous adder design has a better computation delay by approximately 500 ps per addition. In the adder test-bench system the asynchronous adder performance realizes the full overhead delay associated with an asynchronous implementation.