The design of the asynchronous abacus adder

Aim To develop a new high speed and low power adder design scheme for the demand of high speed and low power computing in SOC.Methods A new adder design is proposed in this paper.The adder adopts the Chinese abacus algorithm,combined with asynchronous self-timed techniques,and it also introduces the hybrid handshake protocol in the scheme.It can decrease the number of the carries and increase the parallel computing degrees.So it can achieve high speed while maintaining low power.Results The adder implemented the 0.18μm technique of SMIC.The test result shows the 32-bit asynchronous parallel adder achieves the average computation duration is 0.957ns.Its speed is 7.33 times faster than the synchronous ripple adder,1.517 times faster than the asynchronous ripple adder,and 1.033 times faster than the asynchronous carry-select adder.And its average power is only 25% of the asynchronous carry-select adder.Conclusion The adder design which combine with Chinese abacus algorithm and asynchronous self-timed techniques has good performance on high speed and low power.It has wide implement and develop prospective.