Design and implementation of versatile and reconfigurable multiplier over GF(2~m)

A finite field multiplier architecture is proposed in this paper for ECC.Based on previous digit-serial multiplier architecture,it uses bit-parallel architecture of local parallel to eliminate reduction modulo circuit effectively,and the multiplier architecture also be the same with arbitrary irreducible polynomials.It controlls data format of import by data interface and embedded multiplier of most size,that can configure architecture of finite field multiplier to carry out multiplication operation base on polynomial base.A multiplier proposed in this paper can satisfy different security demand of ECC.