Efficient bit-parallel systolic multiplier over GF (2m)

A bit parallel systolic multiplier in the finite field GF(2m) over the polynomial basis where irreducible polynomial generate the field GF(2m) is presented. The complexity of the proposed multiplier is compared in terms of area, latency and speed. The proposed multiplier has high throughput as compared with the traditional systolic multiplier. Moreover, this multiplier is highly regular, modular, and therefore, well-suited for VLSI implementation with fault tolerant design.