A Fast Finite Field Multiplier Architecture and Its VLSI Implementation

A fast finite field multiplier is proposed in this paper. The architecture equally divides the multiplicator and multiplicand of field multiplication into two sub-polynomials, respectively, whose products are calculated by the digit multiplier. To simplify reduction modulo, special polynomials are used to generate finite field GF(2m), such as AOP (all one polynomials) and trinomials. Compared to the traditional LSD multiplier, the proposed multiplier is two times faster. In addition, this multiplier structure is suitable for VLSI design of high-security cryptographic algorithms.