Research of Design-on-Testability for SoC

A comprehensive survey of the up-to-date design for testability(DFT) methods and testing technologies for system-on-a-chip(SoC) is presented.The very deep sub micrometer technics and the system-on-a-chip (SoC) based on reusable embedded IP(intellectual property) pose new challenges for test,and the new test methodology and strategy for SoC are needed.Some common techniques for VLSI DFT are summarized.The techniques of DFT and testing for embedded cores of digital,analog/mixed-signal,memory,processor and thirdparty IP core are introduced respectively.The DFT strategy of SoC design is discussed.Finally,some future directions in DFT and test technologies for SoC are indicated.