2001Jisuanji gongchengRequires access

VERILOG HDL MODELING

Mingye Liu

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Abstract

Through analyzing the hierarchical modeling, gate-level modeling, dataflow modeling, behavioral modeling and switch-level modeling, this paper expounds the modeling method of Verilog HDL. It is useful to study and use the Verilog HDL, and it is also meaningful to constitute the language standard of Verilog HDL in China.

About this research paper

What this paper is about

Through analyzing the hierarchical modeling, gate-level modeling, dataflow modeling, behavioral modeling and switch-level modeling, this paper expounds the modeling method of Verilog HDL. It is useful to study and use the Verilog HDL, and it is also meaningful to constitute the language standard of Verilog HDL in China.

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Available abstract

Through analyzing the hierarchical modeling, gate-level modeling, dataflow modeling, behavioral modeling and switch-level modeling, this paper expounds the modeling method of Verilog HDL. It is useful to study and use the Verilog HDL, and it is also meaningful to constitute the language standard of Verilog HDL in China.

Key concepts: Computer science, Verilog, Dataflow, Hardware description language, Modeling and simulation, Computer architecture, Programming language, Embedded system

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