VERILOG HDL MODELING
Mingye Liu
Abstract
Mingye Liu
Abstract
Through analyzing the hierarchical modeling, gate-level modeling, dataflow modeling, behavioral modeling and switch-level modeling, this paper expounds the modeling method of Verilog HDL. It is useful to study and use the Verilog HDL, and it is also meaningful to constitute the language standard of Verilog HDL in China.
A significance statement is not available in the OpenAlex record.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
Through analyzing the hierarchical modeling, gate-level modeling, dataflow modeling, behavioral modeling and switch-level modeling, this paper expounds the modeling method of Verilog HDL. It is useful to study and use the Verilog HDL, and it is also meaningful to constitute the language standard of Verilog HDL in China.
Key concepts: Computer science, Verilog, Dataflow, Hardware description language, Modeling and simulation, Computer architecture, Programming language, Embedded system