Design of high￣speed high￣resolution clocked comparator

To guarantee a 10-bit high-resolution for an A/D converter,a high-speed high-resolution clocked comparator circuit is presented with emphasis on analyzing and optimizing the speed and kickback noise.By adding pre-amplifier,a sufficient gain improves the precision of the comparator.The speed is increased by employing two positive-feedback latch circuits.The application of isolation and neutralization techniques restrains the kickback noise.Based on standard TSMC 0.18μm CMOS process,the device was simulated with Cadence Spectre.Results show that the sampling frequency of the comparator is 300MHz,LSB(Least Significant Bit)is±1mV,the propagation delay is 360ps,the power consumption is 2.6mW and the accuracy is 10bit.The circuit is applicable for high-speed high-resolution analog-to-digital converter modules and analog IP core design.