Optimization of Digital System Design Based on FPGA/CPLD Device

Discusses the problem of the optimization of the digital system design based on the FPGA/CPLD device,including the area optimization,thespeed optimization and their relationship.The two area optimization methods,which are the resource sharing of the circuit structure and the serialized method,are illustrated through examples.The principles of three speed optimization me-thods,which are the pipelined design method,the register balanced method and the critical path method are presented.