Study on speed optimization methods in digital system design based on FPGA
YU An-ning
Abstract
YU An-ning
Abstract
The speed optimizing methods in the process of designing digital system based on FPGA device are discussed.Three optimizing methods-pipelined design,low latency and critical path optimization,are researched specifically.By programming some examples in VHDL and comparing the achieved RTL circuit architectures,the results show that the speeds of the digital system are effectively improved after optimization.
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The speed optimizing methods in the process of designing digital system based on FPGA device are discussed.Three optimizing methods-pipelined design,low latency and critical path optimization,are researched specifically.By programming some examples in VHDL and comparing the achieved RTL circuit architectures,the results show that the speeds of the digital system are effectively improved after optimization.
Key concepts: VHDL, Field-programmable gate array, Computer science, Embedded system, Critical path method, Latency (audio), Computer architecture, Process (computing)