ScholarLens Back to search
2004•Journal of Tianjin University Science and TechnologyRequires access

Syntax Equivalence of Verilog HDL and SystemC

Zhigang Cui

Open publisher page 1 citations

Abstract

The syntax equivalence of Verilog HDL and SystemC2.0 is discussed in detail regard to basic syntax structure, timing model, wait and event module and scheduler module. It is concluded that for gate or upper abstract level of Verilog HDL description, there always exists corresponding SystemC description,and it is feasible to develop an EDA design tool to automatically convert Verilog-based IP to SystemC-based IP.

About this research paper

What this paper is about

The syntax equivalence of Verilog HDL and SystemC2.0 is discussed in detail regard to basic syntax structure, timing model, wait and event module and scheduler module. It is concluded that for gate or upper abstract level of Verilog HDL description, there always exists corresponding SystemC description,and it is feasible to develop an EDA design tool to automatically convert Verilog-based IP to SystemC-based IP.

Why it matters

OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

The syntax equivalence of Verilog HDL and SystemC2.0 is discussed in detail regard to basic syntax structure, timing model, wait and event module and scheduler module. It is concluded that for gate or upper abstract level of Verilog HDL description, there always exists corresponding SystemC description,and it is feasible to develop an EDA design tool to automatically convert Verilog-based IP to SystemC-based IP.

Key concepts: SystemC, Verilog, Computer science, Equivalence (formal languages), Programming language, Syntax, Computer architecture, Embedded system

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Syntax Equivalence of Verilog HDL and SystemC — Research Paper | ScholarLens