A FPGA Based I~2C Bus Controller with Sub-address Strobe

In this paper,we propose a FPGA based high-performance I2C bus controller with Sub-address Strobe.Multiple Sub-addresses in I2C bus controllers will certainly benefit system integrating.We first describe the fundamentals and transmission format of I2C bus,then we present the over-all structure of our design using the Top-Down method.We also make behavioral level descriptions of the sub-units using Verilog HDL.The simulation results shows that it can work well at a speed of 400K bit/s.