2004MicroprocessorsRequires access

Design and Implementation of I~2C bus controller for the SAA7111A with FPGA

Sun Guang-fu

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Abstract

In this paper,the specification and timing requirement of I 2C bus are introduced in detail,and an I 2C bus controller for the SAA7111A is designed.The hardware IP core based on FPGA for the full function I 2C bus controller is implemented in VHDL,and an application result is given.

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What this paper is about

In this paper,the specification and timing requirement of I 2C bus are introduced in detail,and an I 2C bus controller for the SAA7111A is designed.The hardware IP core based on FPGA for the full function I 2C bus controller is implemented in VHDL,and an application result is given.

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Available abstract

In this paper,the specification and timing requirement of I 2C bus are introduced in detail,and an I 2C bus controller for the SAA7111A is designed.The hardware IP core based on FPGA for the full function I 2C bus controller is implemented in VHDL,and an application result is given.

Key concepts: Computer science, Field-programmable gate array, VHDL, Control bus, Embedded system, Controller (irrigation), System bus, CAN bus

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Design and Implementation of I~2C bus controller for the SAA7111A with FPGA — Research Paper | ScholarLens