Simulation and realization of FIR filter using modified distributed arithmetic architecture

Aiming at the shortcoming of traditional multiplier occupying larger resource in FPGA,according to the linear characteristics of FIR filter,series Distributed Algorithm(DA),parallel DA,and modified DA are studied.FIR filter is designed based on FPGA by modified DA.High-order FIR filter is achieved in Look-Up Table(LUT) method.16-order FIR is designed by modified DA with Quartus II 7.0.Results show that the modified method can implement FIR filters with the smaller resource usage compared with traditional methods.