ASIP register allocator based on improved graph-coloring algorithm
Yan Xiao-lang Ren Kun
Abstract
Yan Xiao-lang Ren Kun
Abstract
A model was presented to describe the complicated restrictions among registers of application specific instruction processor(ASIP)register file,considering that the traditional graph-coloring register allocation cannot produce optimal code for ASIP with irregular structure.The traditional graph-coloring algorithm was improved to be adapted to ASIP according to this model.In the new algorithm,a directed interference graph was built by analyzing the variables'live range and register constraints.The register allocation was translated into how to simplify this graph.At last the algorithm was applied to an ASIP compiler.Experimental results show that the improved algorithm has better performance of codegeneration and less register spilling than the traditional code-generation algorithm.
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A model was presented to describe the complicated restrictions among registers of application specific instruction processor(ASIP)register file,considering that the traditional graph-coloring register allocation cannot produce optimal code for ASIP with irregular structure.The traditional graph-coloring algorithm was improved to be adapted to ASIP according to this model.In the new algorithm,a directed interference graph was built by analyzing the variables'live range and register constraints.The register allocation was translated into how to simplify this graph.At last the algorithm was applied to an ASIP compiler.Experimental results show that the improved algorithm has better performance of codegeneration and less register spilling than the traditional code-generation algorithm.
Key concepts: Register allocation, Computer science, Graph coloring, Allocator, Parallel computing, Register file, Graph, Algorithm