An efficient technique for exploring register file size in ASIP synthesis

Performance estimation is a crucial operation which drives the design space exploration in Application Speci c Instruction Set Processors (ASIP) synthesis. The usual approach to estimate performance is to do simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. This problem can be solved by scheduler based approaches, which are much faster. However existing scheduler based approaches do not help in exploring storage organization. This paper presents a scheduler based technique for exploring register le size in ASIP synthesis.