A Novel Full Adder with High Speed Low Area

In most of the digital systems adder lies in the critical path that effects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is the main design aspect. The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three transistor XOR gate. Compared to the earlier designed 10, 14, 16 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product.