CMOS Based 1-Bit Full Adder Cell for Low-Power Delay Product

The 1-bit full adder circuit is one of the most important components of any digital system applications. The power-delay product is a measurement of the energy expanded per operational cycle of an arithmetic circuit. This paper presents a new low power full adder based on a new logic approach, which reduces power consumption by implementing full adder using 3T XOR module and 2-to-1 multiplexer, with 8 transistor in total, named CBFA-8T. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.18 µ m technologies. Compared to the earlier designed 10, 12, 16, 28 transistors full adder, the proposed adder shows a significant improvement in silicon area and power delay product. Here Simulation results are performed by TANNER-EDA with 2.3 supply voltage based on 0.18 µ m CMOS technology. The results show that the proposed circuit has the lowest power-delay product with a significant improvement in silicon area and delay than recently proposed full adders in the literature.