Design of High Speed Six Transistor Full Adder using a Novel Two Transistor XOR Gates

In modern era, the number of transistors are reduced in the circuit and ultra low power design have emerged as an active research topic due to its various applications. A full adder is one of the  essential component in digital  circuit design, many improvements have been made to reduce the architecture of a full adder.The main aim of this paper is to reduce the power dissipation and area by redusing the number of transistors.By using general logic of   pmos transistor, the two transistor xor gate can be implemented.  In this paper proposes the novel design of a 2T XOR gate. The design has been compared with earlier proposed 3T, 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An 8-T full adder has been designed using the proposed 2-T XOR gate and its performance has been obtained. the design is simulated in Mentor graphics tool .