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2016•Journal of InstrumentationOpen access

A low noise clock generator for high-resolution time-to-digital convertors

Jeffrey Prinzie, J. Christiaensen, P. Moreira, Michiel S. J. Steyaert, Paul Leroux

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Abstract

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.

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A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.

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Available abstract

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.

Key concepts: Phase-locked loop, Clock generator, Jitter, Voltage-controlled oscillator, PLL multibit, CMOS, Phase noise, Digitally controlled oscillator

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