Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism (NMOS-to-PMOS, PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are: (1) with the exception of PMOS-to-PMOS, pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process. (2) Pulse quenching in general correlates weakly with ion LET, but strongly with incident angle and layout style (i.e. spacing between transistors and n-well contact area). (3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.