2021•Unpublished venueRequires access
Opportunities in 3-D stacked CMOS transistors
M. Radosavljević, C.-Y. Huang, W. Rachmady, S.H. Seung, N. Thomas, G. Dewey, A. Agrawal, K. Owens, C. C. Kuo, C. J. Jezewski, R. Nahm, N. Briggs, T. A. Tronic, T. Michaelos, N. A. Kabir, B. Holybee, K. Jun, P. Morrow, Anh Dang Thuc Phan, S. Shivaraman, Han Wui Then, V. Kapinus, M. K. Harper, P. D. Nguyen, K. L. Cheong, S. Ghose, K. Ganguly, C. Bomberger, Jixiang Tan, M. Abd El Qader, A. Oni, Pamela R. Fischer, R. Bristol, M. Metz, Scott B. Clendenning, B. Turkot, R. Schenker, M. Kobrinsky, J. Kavalieros
Open publisher page 25 citations
Abstract
3-D stacked CMOS transistors offer an opportunity to enable further standard cell and SRAM scaling, making them a promising transistor architecture to extend Moore's law. We review state-of-the-art approaches for achieving 3-D CMOS stacking. The sequential approach is highlighted by fabricating Ge PMOS stacked via layer transfer on top of Si NMOS, and self-aligned approach is demonstrated by simultaneously fabricated NMOS-on-PMOS multi-nanoribbon Si transistors. Both approaches showcase a well-balanced CMOS inverter built from transistors in top and bottom device layers.