DESIGN AND IMPLEMENTATION OF EFFICIENT ADDER BASED FLOATING POINT MULTIPLIER

In this paper a new idea is proposed to increase the speed of single precision floating point multiplier. In floating point multiplication adders are used at different places. The implementation uses efficient adders for compressing the partial products, adding the exponent and at final stage. First different adders are compared based on the delay and then multiplier is designed using the best adder at each stage. The multiplier and the adder modules have been written in Verilog HDL and then synthesized and simulated using Xilinx ISE 14.5 targeted on the Spartan 3E FPGA. The design is verified using chipscopeproanalyzer. Results show that the multiplier speed can be increased if carry save adder is used for adding the partial products and carry select adder for exponent and at final stage.