Implementation of Floating Point Unit based on Booth Multiplier and Compressor Adder

High speed multipliers plays a major role in digital signal processing applications, banking, tax and currency conversions, radar navigation and in real time 3D graphics display. Various techniques have been proposed to design multipliers which are efficient in terms of speed, area and power. Floating point multiplier is better than fixed point multiplier because of wide dynamic range. The floating point multiplier with 3:2 compressor adder and modified booth algorithm is more efficient when compared with other multipliers. Booth technique with compressor adder is used to reduce the partial product in order to increase the speed. This work is implemented in XILINX ISE simulator where the delay and area is improved by 54% and 60.47% in 3:2 compressor adder with modified booth based FPM when compared with compressor adder with modified booth based Floating Point Multiplier, 50% and 40% when compared with compressor adder with Wallace based Floating Point Multiplier and compressor adder based Floating Point Multiplier. Hence speed and area utilized is optimized in 3:2 compressor adder with floating point Multiplier.