VLSI design for an adaptive equalizer using a residue number system architecture for magnetic channels

This paper presents the design of an experimental ASIC for an all-digital adaptive equalizer for magnetic channels. The equalizer design, which is based on an RNS chip architecture, is presented at a system level, with particular attention to choices of word length, scaling, algorithm performance, and specifics of the RNS modules used to implement the LMS adaptive algorithm. It is believed that the short wordlength and high speed requirements of an adaptive equalizer in this particular application make it ideal for an efficient solution through RNS design techniques.