A memory efficient FPGA implementation of quasi-cyclic LDPC decoder

Abstract- Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents an implementation of Quasi-Cyclic Low-Density Parity-Check decoder by using FPGA. Modified Min-Sum decoding algorithm is applied to reduce the memory size needed for information storage. Partially parallel structures, memory management and pipelining schemes are discussed in this paper. Key-Words:- Low-density parity-check (LDPC) codes, VLSI architecture, decoder, Quasi-Cyclic, memory 1