High-throughput and memory efficient LDPC decoder architecture

Abstract: Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents a new kind of high-throughput and memory efficient LDPC decoder architecture. In general, more than fifty percent of memory can be saved over conventional partially parallel decoder architectures. It is shown that this presented hardware structure will be highly competent in high throughput and low decoding latency applications. Key-Words:- Low-density parity-check (LDPC) codes, VLSI architecture, decoder, shift LDPC