An FPGA Implementation of Array LDPC Decoder

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. This paper presents an FPGA implementation of array code based Low-Density Parity-Check code decoder. The advantages of the proposed architecture as compared to the fully parallel or partially parallel architecture are: less memory requirement, avoidance of complex global interconnects and its satisfying throughput. These advantages are derived from exploiting the well-defined structure of the parity check matrix of array code based LDPC codes.