Primitive path delay faults: identification and their use in timing analysis

Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We prove that the maximum primitive PDF delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. From this result, we devise a method to perform timing analysis based on primitive PDF identification which delinks functional analysis from delay computation. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re-identified due to component delay speedup (e.g., post-layout delay optimization). We demonstrate the applicability of our timing analysis approach for a variety of benchmark circuits, and demonstrate the pessimism of conventional floating mode timing analysis approaches in accounting for signal propagation effects.