Provably Correct High-Level Timing Analysis without Path Sensitization

Abstract- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques ei-ther estimate the topological delay of the circuit which may be pes-simistic, or use gate-level timing analysis for calculating the true de-lay, which may be prohibitively expensive. We show that the paths in the implementation of a behavioral spec-ification can be partitioned into two sets, SP and UP. While the paths in SP can affect the delay of the circuit, the paths in UP cannot. Con-sequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in SP, eliminating the need for the computationally intensive process of path sensitiza-tion. Experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation be-comes computationally infeasible. The high-level delay estimates are verified by comparing with delay estimates obtained by gate-level tim-ing analysis on the actual implementation. I.