Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits

The propagation delay of interlayer 3D interconnects is investigated in this paper. For RC interconnects connecting two circuits located on different physical planes, the interconnect delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore delay model is described as a geometric program. Simulations indicate delay improvements of up to 26% for relatively short interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of delay and power consumption