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A Study of Snapback and Parasitic Bipolar Action for ESD NMOS Modeling

Jia Hai Lu, Yuxi Jiang, Dian Yang, Ran Feng

Open publisher page 4 citations

Abstract

A study has been done on the snapback and parasitic bipolar action for modeling ESD NMOS in this paper. A DC model for ESD NMOS is provided, which includes a MOS transistor extracted from BSIM 3V3, a bipolar transistor for parasitic effect, substrate resistance and series resistance. Equations for modeling the high current behavior of NMOS transistor have been developed. Extraction methodology for obtaining the bipolar parameters is given. Simulation results are presented and compared to the testing data for 0.6um NMOS.

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What this paper is about

A study has been done on the snapback and parasitic bipolar action for modeling ESD NMOS in this paper. A DC model for ESD NMOS is provided, which includes a MOS transistor extracted from BSIM 3V3, a bipolar transistor for parasitic effect, substrate resistance and series resistance. Equations for modeling the high current behavior of NMOS transistor have been developed. Extraction methodology for obtaining the bipolar parameters is given. Simulation results are presented and compared to the testing data for 0.6um NMOS.

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Available abstract

A study has been done on the snapback and parasitic bipolar action for modeling ESD NMOS in this paper. A DC model for ESD NMOS is provided, which includes a MOS transistor extracted from BSIM 3V3, a bipolar transistor for parasitic effect, substrate resistance and series resistance. Equations for modeling the high current behavior of NMOS transistor have been developed. Extraction methodology for obtaining the bipolar parameters is given. Simulation results are presented and compared to the testing data for 0.6um NMOS.

Key concepts: NMOS logic, Snapback, Electrostatic discharge, Bipolar junction transistor, Transistor, Materials science, Electronic engineering, Electrical engineering

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