A programmable oversampling sigma-delta analog-to-digital converter

In this paper, an oversampling sigma-delta analog-to-digital converter (ADC) has been designed and implemented in 1.5 /spl mu/m n-well CMOS process using a 1st order modulator and a 2nd order cascaded integrator comb (CIC) decimation filter. The modulator, which is the analog part of the ADC, has been designed using floating gate MOSFETs, which offers a higher common mode range for analog signals. The decimation filter is a digital low pass filter and can be programmed to give 7-bit and 10-bit digital outputs depending upon the oversampling ratio of 16 and 64, respectively. The ADC can be operated up to a clock sampling frequency of 8 MHz.