High resolution Audio용 ΣΔ Analog to Digital Converter를 위한 Digital Decimation filter 설계

Digital decimation filter is inevitable in oversampling sigma-delta A/D converters for the sake of reducing the oversampling rate to audio sampling rate. This paper propose a Verilog design and implementation of an area-efficient, high performance digital decimation filter that provides advantage for sigma-delta analog to digital converters. The digital decimation filter consists of two cascaded CIC(cascaded integrator-comb) filter and half-band FIR filters. FIR Filter coefficients is used to reduce hardware complexity of multiplication. This three-stage decimation filter is designed in 0.18-㎛ CMOS technology. Final design shows that it incorporates 1 ㎟ of active area including audio interface with stereo decimation filter structure, shows 2mA power consumption at clock rate of 12.288MHz. Simulation results show that this digital decimation filter is suitable for high performance digital audio decimation filters.