Design of a reconfigurable digital decimation filter for flexible GNSS receivers

This paper presents a reconfigurable decimation filter architecture for reconfigurable multiband GNSS receivers. The proposed filter architecture is designed for a reconfigurable GNSS subsampling receiver, where the sampling process is performed at the Analog to Digital Converter. As the selected sampling rates are much higher than the Nyquist rate, a decimation stage is required to speed up GNSS digital processing, mainly the acquisition, the tracking and the navigation. The proposed reconfigurable filter performs decimation in two stages; the first one is a Cascade Integrator Combs (CIC). This filter allows reducing the sampling rate to twice the required GNSS signals bandwidth. The second stage composed of compensation filter to achieve wide broadband compensation of the CIC filter and to perform decimation to the Nyquist frequency. In this paper, Decimation filter specification for multiband GNSS signals is first derived. Then, the parameters of CIC and FIR filters are investigated through simulations under Matlab.