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2002•Unpublished venueRequires access

Object oriented ARM7 coprocessor

Giuliano Donzellini, S. Nervi, D. Ponta, S. Rossi, Stefano Rovetta

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Abstract

This paper presents preliminary results on the design of an Object Coprocessor (OCP) cooperating with a RISC-architecture processor (ARM7, by Advanced RISC Machines Ltd). This coprocessor implements in hardware some low-level processing and control steps required by the object-oriented model. The processor and the OCP constitute a processing architecture whose extended instruction set features "object" treatment capabilities. Some special coprocessor instruction codes ("Object Instructions") have been introduced. Concepts such as "Polymorphism" and "Virtual methods" are supported at the hardware level. Preliminary results using typical object-oriented sequences show a gain in speed over a pure software implementation, on the same RISC machine. The specific design presented here refers to a prototype implementation that is currently under development and supported by the European Union Esprit Project (7517 SUMIS).

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What this paper is about

This paper presents preliminary results on the design of an Object Coprocessor (OCP) cooperating with a RISC-architecture processor (ARM7, by Advanced RISC Machines Ltd). This coprocessor implements in hardware some low-level processing and control steps required by the object-oriented model. The processor and the OCP constitute a processing architecture whose extended instruction set features "object" treatment capabilities. Some special coprocessor instruction codes ("Object Instructions") have been introduced. Concepts such as "Polymorphism" and "Virtual methods" are supported at the hardware level. Preliminary results using typical object-oriented sequences show a gain in speed over a pure software implementation, on the same RISC machine. The specific design presented here refers to a prototype implementation that is currently under development and supported by the European Union Esprit Project (7517 SUMIS).

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Available abstract

This paper presents preliminary results on the design of an Object Coprocessor (OCP) cooperating with a RISC-architecture processor (ARM7, by Advanced RISC Machines Ltd). This coprocessor implements in hardware some low-level processing and control steps required by the object-oriented model. The processor and the OCP constitute a processing architecture whose extended instruction set features "object" treatment capabilities. Some special coprocessor instruction codes ("Object Instructions") have been introduced. Concepts such as "Polymorphism" and "Virtual methods" are supported at the hardware level. Preliminary results using typical object-oriented sequences show a gain in speed over a pure software implementation, on the same RISC machine. The specific design presented here refers to a prototype implementation that is currently under development and supported by the European Union Esprit Project (7517 SUMIS).

Key concepts: Coprocessor, Reduced instruction set computing, Computer science, Instruction set, Object (grammar), Computer architecture, Software, Embedded system

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