Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA

Reduced Instruction Set (RISC) architectures optimize a complex ISA by implementing only the most frequently used instructions in hardware; however, the application execution time significantly increases when executing heavily used instructions in software. One technique that optimizes the trade-off of implementation cost and execution time is the use of a Multiprocessor System-on-Chip (MPSoC), in which RISC processors extend their ISA by sharing coprocessors that implement lesser-used instructions. This article analyses the impact of shared coprocessor failures on two RISC-V MPSoC architectures. We evaluated these architectures using two image processing applications and four failure rates in terms of power dissipation, energy consumption, area consumption, maximum operating frequency, and execution time. The experiments show a 16% maximum increase in execution time for the application with a low percentage of instructions executed. In contrast, for the application with the highest rate of coprocessor use, considering a one-fault scenario, the execution time does not increase significantly in one of the architectural configurations proposed for the MPSoC.