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2023•Unpublished venueRequires access

An Area Optimized Floating-Point Coprocessor for RISC-V Processor

G P Gayathri, S Jaya, Krishnakumar Rao S

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Abstract

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.

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What this paper is about

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.

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Available abstract

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.

Key concepts: Coprocessor, Reduced instruction set computing, Floating-point unit, Computer science, Floating point, Parallel computing, Embedded system, Instruction set

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